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distrib > Mageia > 8 > i586 > by-pkgid > be2a7a2881fec033114853d706c3b934 > files > 2

cpl-7.1.2-1.mga8.src.rpm

diff -ur cpl-7.1/cplcore/cpl_image_basic.c cpl-7.1.m/cplcore/cpl_image_basic.c
--- cpl-7.1/cplcore/cpl_image_basic.c	2018-01-29 14:30:11.000000000 +0100
+++ cpl-7.1.m/cplcore/cpl_image_basic.c	2018-10-03 19:51:09.774695270 +0200
@@ -225,10 +225,10 @@
 
 #undef CPL_OPERATION
 
-#ifdef __SSE3__
+#if (defined __SSE3__) && (defined __x86_64)
 #include <pmmintrin.h>
 #endif
-#ifdef __SSE2__
+#if (defined __SSE2__) && (defined __x86_64)
 #include <xmmintrin.h>
 
 #ifdef __clang__
@@ -236,11 +236,11 @@
 #  else
 #    define cpl_m_from_int64 _m_from_int64
 #  endif
-#endif
+#endif /* clang */
 
-#if defined __SSE2__ || defined __SSE3__
+#if (defined __SSE2__ || defined __SSE3__) && (defined __x86_64)
 
-#if defined __SSE3__
+#if (defined __SSE3__) && (defined __x86_64)
 #define CPL_MM_ADDSUB_PS(a, b) _mm_addsub_ps(a, b)
 #define CPL_MM_ADDSUB_PD(a, b) _mm_addsub_pd(a, b)
 #else
@@ -251,7 +251,7 @@
 #define CPL_MM_ADDSUB_PD(a, b) \
   _mm_add_pd(a, _mm_xor_pd(b, (__m128d)_mm_set_epi64(cpl_m_from_int64(0x0llu), \
                                                      cpl_m_from_int64(0x8000000000000000llu))))
-#endif
+#endif /* SSE3**/
 
 static cpl_error_code cpl_image_multiply_fcomplex_sse_(cpl_image       *,
                                                        const cpl_image *)
@@ -259,7 +259,7 @@
 static cpl_error_code cpl_image_multiply_dcomplex_sse_(cpl_image       *,
                                                        const cpl_image *)
     CPL_ATTR_NONNULL;
-#endif
+#endif //AA
 
 /*-----------------------------------------------------------------------------
                             Function codes
@@ -714,7 +714,7 @@
 {
     /* Faster version of code generated with gcc -ffast-math */
     /* (NaNs and other float specials are no longer IEEE compliant) */
-#if (defined __SSE3__ || defined __SSE2__)
+#if (defined __SSE3__ || defined __SSE2__) && (defined __x86_64)
     cpl_ensure_code(im1     != NULL, CPL_ERROR_NULL_INPUT);
     cpl_ensure_code(im2     != NULL, CPL_ERROR_NULL_INPUT);
 
@@ -3780,7 +3780,7 @@
 }
 
 
-#if (defined __SSE3__ || defined __SSE2__)
+#if (defined __SSE3__ || defined __SSE2__) && (defined __x86_64)
 
 
 /*----------------------------------------------------------------------------*/
diff -ur cpl-7.1/cplcore/cpl_mask.c cpl-7.1.m/cplcore/cpl_mask.c
--- cpl-7.1/cplcore/cpl_mask.c	2018-01-29 14:30:10.000000000 +0100
+++ cpl-7.1.m/cplcore/cpl_mask.c	2018-10-03 19:59:18.736108540 +0200
@@ -43,7 +43,7 @@
 
 #include <assert.h>
 
-#ifdef __SSE2__
+#if (defined __SSE2__) && (defined __x86_64)
 #include <emmintrin.h>
 
 #ifdef __clang__
@@ -84,7 +84,7 @@
 
 #define CPL_MASK_NOT8 (((((((((((((((cpl_bitmask)CPL_BINARY_1<<8) | (cpl_bitmask)CPL_BINARY_1) <<8) | (cpl_bitmask)CPL_BINARY_1)<<8) | (cpl_bitmask)CPL_BINARY_1 )<<8)|(cpl_bitmask)CPL_BINARY_1)<<8) | (cpl_bitmask)CPL_BINARY_1) <<8) | (cpl_bitmask)CPL_BINARY_1)<<8) | (cpl_bitmask)CPL_BINARY_1)
 
-#ifdef __SSE2__
+#if (defined __SSE2__) && (defined __x86_64)
 #define CPL_MASK_REGISTER_SIZE 16
 #define CPL_MASK_REGISTER_TYPE __m128i
 #else