Sophie

Sophie

distrib > Mageia > 9 > armv7hl > media > core-release-src > by-pkgid > c61617a19919cc3f036b60db7823a40e > files > 2

cpl-7.2.2-2.mga9.src.rpm

diff --git a/cplcore/cpl_image_basic.c b/cplcore/cpl_image_basic.c
index 8f11dc6..a702504 100644
--- a/cplcore/cpl_image_basic.c
+++ b/cplcore/cpl_image_basic.c
@@ -226,10 +226,10 @@ static cpl_error_code cpl_fft(double *, double *, const unsigned *, int, int);
 
 #undef CPL_OPERATION
 
-#ifdef __SSE3__
+#if (defined __SSE3__) && (defined __x86_64)
 #include <pmmintrin.h>
 #endif
-#ifdef __SSE2__
+#if (defined __SSE2__) && (defined __x86_64)
 #include <xmmintrin.h>
 
 #ifdef __clang__
@@ -237,11 +237,11 @@ static cpl_error_code cpl_fft(double *, double *, const unsigned *, int, int);
 #else
 #define cpl_m_from_int64 _m_from_int64
 #endif
-#endif
+#endif /* clang */
 
-#if defined __SSE2__ || defined __SSE3__
+#if (defined __SSE2__ || defined __SSE3__) && (defined __x86_64)
 
-#if defined __SSE3__
+#if (defined __SSE3__) && (defined __x86_64)
 #define CPL_MM_ADDSUB_PS(a, b) _mm_addsub_ps(a, b)
 #define CPL_MM_ADDSUB_PD(a, b) _mm_addsub_pd(a, b)
 #else
@@ -253,7 +253,7 @@ static cpl_error_code cpl_fft(double *, double *, const unsigned *, int, int);
     _mm_add_pd(a, _mm_xor_pd(b, (__m128d)_mm_set_epi64(       \
                                     cpl_m_from_int64(0x0llu), \
                                     cpl_m_from_int64(0x8000000000000000llu))))
-#endif
+#endif /* SSE3**/
 
 static cpl_error_code
 cpl_image_multiply_fcomplex_sse_(cpl_image *,
@@ -709,7 +709,7 @@ cpl_error_code cpl_image_multiply(cpl_image *im1, const cpl_image *im2)
 {
     /* Faster version of code generated with gcc -ffast-math */
     /* (NaNs and other float specials are no longer IEEE compliant) */
-#if (defined __SSE3__ || defined __SSE2__)
+#if (defined __SSE3__ || defined __SSE2__) && (defined __x86_64)
     cpl_ensure_code(im1 != NULL, CPL_ERROR_NULL_INPUT);
     cpl_ensure_code(im2 != NULL, CPL_ERROR_NULL_INPUT);
 
@@ -3832,8 +3832,7 @@ cpl_vector_get_fwhm(const cpl_vector *vec, cpl_size pos, double half_max)
 }
 
 
-#if (defined __SSE3__ || defined __SSE2__)
-
+#if (defined __SSE3__ || defined __SSE2__) && (defined __x86_64)
 
 /*----------------------------------------------------------------------------*/
 /**
diff --git a/cplcore/cpl_mask.c b/cplcore/cpl_mask.c
index 3e6be96..5126fd7 100644
--- a/cplcore/cpl_mask.c
+++ b/cplcore/cpl_mask.c
@@ -46,7 +46,7 @@
 
 #include <assert.h>
 
-#ifdef __SSE2__
+#if (defined __SSE2__) && (defined __x86_64)
 #include <emmintrin.h>
 
 #ifdef __clang__
@@ -116,7 +116,7 @@
       << 8) |                                                                  \
      (cpl_bitmask)CPL_BINARY_1)
 
-#ifdef __SSE2__
+#if (defined __SSE2__) && (defined __x86_64)
 #define CPL_MASK_REGISTER_SIZE 16
 #define CPL_MASK_REGISTER_TYPE __m128i
 #else