From cbe631dbd334fa0aa6de3656e89b6b71551719c2 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang <zhenyu.z.wang@intel.com> Date: Thu, 11 Sep 2008 16:14:47 +0800 Subject: [PATCH] Add support for G41 chipset G41 is another 4 series chipset like G45/43. --- src/common.h | 7 ++++++- src/i810_driver.c | 4 ++++ src/i830_driver.c | 5 +++++ 3 files changed, 15 insertions(+), 1 deletions(-) diff --git a/src/common.h b/src/common.h index f2ae502..98d4c9f 100644 --- a/src/common.h +++ b/src/common.h @@ -323,6 +323,11 @@ extern int I810_DEBUG; #define PCI_CHIP_Q45_G_BRIDGE 0x2E10 #endif +#ifndef PCI_CHIP_G41_G +#define PCI_CHIP_G41_G 0x2E32 +#define PCI_CHIP_G41_G_BRIDGE 0x2E30 +#endif + #if XSERVER_LIBPCIACCESS #define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr #define VENDOR_ID(p) (p)->vendor_id @@ -355,7 +360,7 @@ extern int I810_DEBUG; #define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G) #define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME) #define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM) -#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G) +#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G) #define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME) #define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_GM45(pI810) || IS_G4X(pI810)) #define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\ diff --git a/src/i810_driver.c b/src/i810_driver.c index 8540646..36b6474 100644 --- a/src/i810_driver.c +++ b/src/i810_driver.c @@ -156,6 +156,7 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ), + INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ), { 0, 0, 0 }, }; @@ -212,6 +213,7 @@ static SymTabRec I810Chipsets[] = { {PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"}, {PCI_CHIP_G45_G, "G45/G43"}, {PCI_CHIP_Q45_G, "Q45/Q43"}, + {PCI_CHIP_G41_G, "G41"}, {-1, NULL} }; @@ -245,6 +247,7 @@ static PciChipsets I810PciChipsets[] = { {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA}, {PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA}, {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA}, + {PCI_CHIP_G41_G, PCI_CHIP_G41_G, RES_SHARED_VGA}, {-1, -1, RES_UNDEFINED } }; @@ -812,6 +815,7 @@ I810Probe(DriverPtr drv, int flags) case PCI_CHIP_IGD_E_G: case PCI_CHIP_G45_G: case PCI_CHIP_Q45_G: + case PCI_CHIP_G41_G: xf86SetEntitySharable(usedChips[i]); /* Allocate an entity private if necessary */ diff --git a/src/i830_driver.c b/src/i830_driver.c index 637bb44..a04248c 100644 --- a/src/i830_driver.c +++ b/src/i830_driver.c @@ -255,6 +255,7 @@ static SymTabRec I830Chipsets[] = { {PCI_CHIP_IGD_E_G, "Intel Integrated Graphics Device"}, {PCI_CHIP_G45_G, "G45/G43"}, {PCI_CHIP_Q45_G, "Q45/Q43"}, + {PCI_CHIP_G41_G, "G41"}, {-1, NULL} }; @@ -282,6 +283,7 @@ static PciChipsets I830PciChipsets[] = { {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, RES_SHARED_VGA}, {PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA}, {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA}, + {PCI_CHIP_G41_G, PCI_CHIP_G41_G, RES_SHARED_VGA}, {-1, -1, RES_UNDEFINED} }; @@ -1230,6 +1232,9 @@ i830_detect_chipset(ScrnInfoPtr pScrn) case PCI_CHIP_Q45_G: chipname = "Q45/Q43"; break; + case PCI_CHIP_G41_G: + chipname = "G41"; + break; default: chipname = "unknown chipset"; break; -- 1.6.0.2