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>ioremap_nocache</SPAN
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><H2
>Name</H2
>ioremap_nocache -- map bus memory into CPU space
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>Synopsis</H2
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><CODE
><CODE
CLASS="FUNCDEF"
>void * <TT
CLASS="FUNCTION"
>ioremap_nocache </TT
></CODE
>(unsigned long <TT
CLASS="PARAMETER"
><I
>offset</I
></TT
>, unsigned long <TT
CLASS="PARAMETER"
><I
>size</I
></TT
>);</CODE
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><H2
>Arguments</H2
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><DT
><TT
CLASS="PARAMETER"
><I
>offset</I
></TT
></DT
><DD
><P
> bus address of the memory
</P
></DD
><DT
><TT
CLASS="PARAMETER"
><I
>size</I
></TT
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><DD
><P
> size of the resource to map
</P
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><H2
>Description</H2
><P
> ioremap_nocache performs a platform specific sequence of operations to
make bus memory CPU accessible via the readb/readw/readl/writeb/
writew/writel functions and the other mmio helpers. The returned
address is not guaranteed to be usable directly as a virtual
address.
</P
><P
> This version of ioremap ensures that the memory is marked uncachable
on the CPU as well as honouring existing caching rules from things like
the PCI bus. Note that there are other caches and buffers on many
busses. In paticular driver authors should read up on PCI writes
</P
><P
> It's useful if some control registers are in such an area and
</P
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