--- FSMDesigner4-1.2/src/genverilog/Makefile.am	2008-02-01 08:20:33.000000000 -0800
+++ FSMDesigner4-1.2/src/genverilog/Makefile.am.new	2008-12-19 17:31:05.000000000 -0800
@@ -1,6 +1,6 @@
 bin_PROGRAMS = fsmveriloggeneration
 
-INCLUDES = @QT_CFLAGS@ @XERCES_CFLAGS@
+INCLUDES = @QT_CFLAGS@
 LDADD= @QT_LIBS@ ../core/libcore.la ../xmlcreate/libxmlloadstore.la @XERCES_LDFLAGS@
 
 %.h: %.ui
@@ -14,4 +14,4 @@
 
 
 
-fsmveriloggeneration_SOURCES = ../verification/verify.cpp ../verification/verify.h ../core_I.h ../fsm_I.h ../load_I.h ../corefactory.cpp ../corefactory.h ../loadfactory.h ../loadfactory.cpp genverilog.cpp generationofverilog.h generationofverilog.cpp ../verification/logicmin.cpp ../verification/logicmin.h ../verification/errordetailswindow.h ../verification/errordetailswindow.cpp ../verification/invertDNF.cpp ../verification/invertDNF.h
\ No newline at end of file
+fsmveriloggeneration_SOURCES = ../verification/verify.cpp ../verification/verify.h ../core_I.h ../fsm_I.h ../load_I.h ../corefactory.cpp ../corefactory.h ../loadfactory.h ../loadfactory.cpp genverilog.cpp generationofverilog.h generationofverilog.cpp ../verification/logicmin.cpp ../verification/logicmin.h ../verification/errordetailswindow.h ../verification/errordetailswindow.cpp ../verification/invertDNF.cpp ../verification/invertDNF.h