Description:

Verilog::Parser, Verilog::Preproc, and other Perl modules useful for
manipulation of Verilog files. The Verilog::Parser package will
tokenize a Verilog file when the parse() method is called and invoke
various callback methods. This is useful for extracting information
and editing files while retaining all context. For netlist like
extractions, see Verilog::Netlist. Verilog::Preproc reads Verilog
files, and preprocesses them according to the Verilog 2001
specification. Programs can be easily converted from reading a
IO::File into reading preprocessed output from Verilog::Preproc.
Verilog::Netlist contains interconnect information about a whole
design database.